Search - DDS FPGA

[VHDL-FPGA-Verilog] 基于FPGA的直接数字合成器设计

Description: 1、利用FLEX10的片内RAM资源，根据DDS原理，设计产生正弦信号的各功能模块和顶层原理图； 2、利用实验板上的TLC7259转换器，将1中得到的正弦信号，通过D/A转换，通过ME5534滤波后在示波器上观察； 3、输出波形要求：在输入时钟频率为16KHz时，输出正弦波分辨率达到1Hz；在输入时钟频率为4MHz时，输出正弦波分辨率达到256Hz； 4、通过RS232C通信，实现FPGA和PC机之间串行通信，从而实现用PC机改变频率控制字，实现对输出正弦波频率的控制。-a use FLEX10-chip RAM resources, in accordance with DDS principle, design sinusoidal signal generated by the top-level functional modules and schematics; 2, the experimental board TLC7259 converters, will be a sinusoidal signal, the D/A conversion, after filtering through the ME5534 oscilloscope observation; 3, the output waveform requirements : the input clock frequency of 16KHz, sine wave output resolution of 1Hz; the input clock frequency of 4MHz, the sine wave output resolution of 256Hz; 4, RS232C communications, FPGA and PC serial communications between in order to achieve PC-frequency control characters, the realization of sine wave output frequency control.
Platform: | Size: 21504 | Author: 竺玲玲 | Hits:

[Communication-Mobile] DDS+PLL

Description: 基于FPGA的新的DDS+PLL时钟发生器-FPGA-based new DDS PLL clock generator
Platform: | Size: 145408 | Author: 李敏 | Hits:

[Communication] Project1-DDS

Description: 直接频率和成DDS，可以在Altera的FPGA下载实现-directly into DDS frequency and can be downloaded from Altera FPGA Implementation
Platform: | Size: 8192 | Author: lf | Hits:

[SCM] DDS+51

Description: 本程序功能: DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-this program functions : DDS folder procedures, complete direct digital frequency synthesis, sine, triangle, Three square waveform, and can sweep. can be set up through the keyboard operation frequency waveform parameters and the types of choice and control operations. composed of two parts, "C" folder, for the 51 microcontroller running C Programming Language, "Verilog" folder, use the Verilog language FPGA procedures.
Platform: | Size: 1027072 | Author: 吴健 | Hits:

[Software Engineering] DDS_F_PGA

Description: DDS的FPGA实现文章做FPGA和DDS的一参拷-DDS FPGA articles do FPGA and DDS a Senate emboss
Platform: | Size: 46080 | Author: sunny_girl | Hits:

[VHDL-FPGA-Verilog] dds

Description: 用FPGA实现DDS,可变频,幅值由硬件完成-Using FPGA realize DDS, can be frequency, amplitude from hardware to complete
Platform: | Size: 674816 | Author: liuyu | Hits:

[SCM] FPGA--DDS-PhaseMeasure

Description: Verilog实现的DDS正弦信号发生器和测频测相模块，DDS模块可产生两路频率和相位差均可预置调整的值正弦波，频率范围为20Hz-5MHz，相位范围为0°-359°，测量的数据通过引脚传输给单片机，单片机进行计算和显示。-Verilog realize the DDS sine wave signal generator and frequency measurement module test phase, DDS module can generate both frequency and phase difference can be preset to adjust the value of sine wave, frequency range of 20Hz-5MHz, phase range of 0 °-359 ° , measurement data and transmit them to the single-chip pin, single-chip microcomputer to calculate and display.
Platform: | Size: 1371136 | Author: haoren | Hits:

[VHDL-FPGA-Verilog] DDS-2

Description: 用FPGA实现DDS的原理图，结构清晰，采用总线方式与外部单片机通信-FPGA realization of DDS with the schematic diagram, structural clarity, the use of bus-way communication with the outside Singlechip
Platform: | Size: 13312 | Author: 赵培立 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 用51和 FPGA实现的 DDS的程序-FPGA with 51 and realize the process of DDS
Platform: | Size: 5120 | Author: 胡玉贵 | Hits:

[SCM] DDs

Description: 此为DDS的单片机程序，已经得以实现，请放心。-This is the single-chip DDS procedures, has been able to realize, please rest assured.
Platform: | Size: 1024 | Author: 李旸 | Hits:

[Other] dds

Description: FPGA实现直接数字信号源.一个相位累加器的设计-FPGA realization of direct digital signal source. A phase accumulator design
Platform: | Size: 5120 | Author: 马彩青 | Hits:

[Program doc] DDS

Description: FPGA中实现基于查找表方式（LUT）的DDS实现，可用在数字下变频和COSTAS锁相环中，Verilog编写，本人已经调通-In FPGA-based lookup table approach (LUT) to achieve the DDS can be used in the digital down-conversion and COSTAS PLL, Verilog prepared, I have transferred Qualcomm
Platform: | Size: 148480 | Author: | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于飓风1 fpga 和stc单片机的dds信号源程序是自己些的能用最大频率是2M-1 fpga based on the hurricane and STC dds SCM signal source more of their own can use the maximum frequency is 2M
Platform: | Size: 362496 | Author: 阿斯顿 | Hits:

[VHDL-FPGA-Verilog] dds

Description: DDS正弦信号发生器频率和相位连续可调。频率最大2M
Platform: | Size: 3072 | Author: dsf | Hits:

[SCM] Verilog

Description: DDS，FPGA产生，用verilog语言实现-DDS, FPGA generated using Verilog language
Platform: | Size: 25600 | Author: | Hits:

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[VHDL-FPGA-Verilog] 基于FPGA的直接数字合成器设计

[Communication-Mobile] DDS+PLL

[Communication] Project1-DDS

[SCM] DDS+51

[Software Engineering] DDS_F_PGA

[VHDL-FPGA-Verilog] dds

[SCM] FPGA--DDS-PhaseMeasure

[VHDL-FPGA-Verilog] DDS-2

[VHDL-FPGA-Verilog] DDS

[SCM] DDs

[Other] dds

[Program doc] DDS

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] dds

[SCM] Verilog

[VHDL-FPGA-Verilog] vhdl-dds

[VHDL-FPGA-Verilog] dds

[Software Engineering] DDS

[VHDL-FPGA-Verilog] DDS-FPGA

[VHDL-FPGA-Verilog] dds(1)

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